Logic debugging by replacing internal gates with new functions

Relatore:  Masahiro Fujita - University of Tokyo
  lunedì 14 settembre 2015 alle ore 11.00 10:45 rinfresco, 11:00 inizio seminario
First we present a general QBF (Quantified Boolean Formula)-based formulation and its SAT-based solver which can be applied to partial logic synthesis. It can deal with problems including logic debugging, test pattern generation for multiple functional faults and logic optimization. Then we show its application and extension for logic debugging by replacing internal gates with new appropriate functions. We describe experiences on debugging industrial circuits, and based on them define different problems: replacing only functions of internal gates (no change in circuit topology), replacing internal gates with new functions of primary inputs, and replacing internal gates with new functions of internal signals. The last one is the most general approach for logic debugging, but needs new formulations. A new search method for good internal signals as inputs to the replacing functions, which is based on QBF formulation, is presented. This method is quite different from the previous ones in the sense that it searches not only for appropriate functions which replace the target gates, but also their inputs out of all internal signals.

Ca' Vignal 2, Piano 1°, Aula L

Tiziano Villa

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Data pubblicazione
31 agosto 2015

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