Towards Correctness-Constrained Execution for Processor Designs

Every integrated circuit is released with latent bugs. The damage and
risk implied by an escaped bug ranges from almost imperceptible to
potential tragedy; unfortunately it is impossible to discern within
this range before a bug has been exposed and analyzed.
While the past few decades have witnessed significant efforts to
improve verification methodology for hardware systems, these efforts
have been far outstripped by the massive complexity of modern
digital designs, leading to product releases for which an always
smaller fraction of system's states has been verified.
The news of escaped bugs in large market designs and/or safety
critical domains is alarming because of safety and cost implications
(due to replacements, lawsuits, etc.).
This talk will describe our solutions to solve the verification
challenge, such that users of future designs can be assured that
their devices can operate completely free of bugs. We will attack the
problem both at design-time, by presenting techniques to boost the
fraction of the state space that can be verified before tape-out,
and after deployment in the field, discussing novel solutions which can
correct escaped bugs after a system has been shipped. Our ultimate
vision for this technology is to make hardware as malleable as software.