Modeling, Simulation and Validation of System-On-Chip
- Modeling, Simulation and Validation of System-On-Chip
The project aims at defining a
testing methodology that is able to cover the whole
SoC (System on Chip) design flow from the system-level down to the structural one,
and that uses the same error model and test generation technique.
CSS e script comuni siti DOL - frase 9957