Alessandro Venturelli

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alessandro|venturelli*univr|it <== Replace | with . and * with @ to have the right email address.
Not present since
December 31, 2010
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Research interests
Topic Description Research area
Embedded system design Design techniques for the automatic generation of embedded hardware/software starting from transactional level models (TLM) and with emphasis on: - TLM-RTL synthesis and abstraction - RTL-to-SW abstraction - TLM transactor generation - Device-driver generation - Embedded SW for multicore systems - Hardware description language-based modeling - Middleware-based design Cyber-physical systems
Embedded and cyber-physical systems
Projects
Title Starting date
Modellazione e verifica di sistemi embedded 11/26/09
Sviluppo degli ambienti di progettazione per sistemi embedded HIFSuite e ZigBeeSuite 11/7/08





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