Luigi Di Guglielmo

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luigi|diguglielmo*univr|it <== Replace | with . and * with @ to have the right email address.
Not present since
December 31, 2017
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Modules

Modules running in the period selected: 1.
Click on the module to see the timetable and course details.

Course Name Total credits Online Teacher credits Modules offered by this teacher
Bachelor's degree in Computer Science Operating Systems (2011/2012)   12    4  [Laboratorio 1 e 2] (Laboratorio)

 

Research groups

Electronic Systems Design (ESD)
Techniques for the automatic design of electronic systems, based on formal languages and correct by construction or formally verified methodologies
Research interests
Topic Description Research area
Embedded system verification Verification techniques for embedded systems at different abstraction levels, with particular emphasis on: - Static verification - Dynamic verification - Semi-formal verification - Hybrid and real-time systems Cyber-physical systems
Hardware validation
Projects
Title Starting date
Progettazione di sistemi digitali basati su strutture logiche regolari (PRIN 2009) 7/15/11
Verifica formale di Software modellato e generato automaticamente (Verilab - Azione I) 10/14/10
Verifica formale di Software modellato e generato automaticamente (Verilab - Azione III) 10/14/10
Verifica formale di Software modellato e generato automaticamente (Verilab - Azione V) 10/14/10
Modellazione e verifica di sistemi embedded 11/26/09
Sviluppo degli ambienti di progettazione per sistemi embedded HIFSuite e ZigBeeSuite 11/7/08
C4C - Control for Coordination of Distributed Systems 5/1/08
COCONUT - A correct-by Construction Workbench for Design and Verification of Embedded Systems 1/1/08




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