Giuseppe  Di Guglielmo

The contents of this page are the responsibility of the person: Giuseppe Di Guglielmo
In caso di assenza rivolgersi alla struttura: Department of Computer Science

GDG,  September 28, 2012
Qualification
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Mobile
+39 347 0493371

E-mail
giuseppe|diguglielmo*univr|it <== Replace | with . and * with @ to have the right email address.

Personal web page
http://www.cs.columbia.edu/~giuseppe

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Research groups
Name Description
Electronic Systems Design (ESD) Techniques for the automatic design of electronic systems, based on formal languages and correct by construction or formally verified methodologies

Skills
Topic Description Research area
Embedded system verification Verification techniques for embedded systems at different abstraction levels, with particular emphasis on: - Static verification - Dynamic verification - Semi-formal verification - Hybrid and real-time systems Sistemi ciberfisici
Hardware - Hardware validation

Research products

Year
Type of item
Number of research products per page
publications on 32 total
 

Projects
Title Starting date
Verifica formale di Software modellato e generato automaticamente (Verilab - Azione I) 10/14/10
Verifica formale di Software modellato e generato automaticamente (Verilab - Azione III) 10/14/10
Verifica formale di Software modellato e generato automaticamente (Verilab - Azione V) 10/14/10
Modellazione e verifica di sistemi embedded 11/26/09
Centre of Reserach Excellence in Dependable Embedded Systems (CREDES) 10/1/09
Sviluppo degli ambienti di progettazione per sistemi embedded HIFSuite e ZigBeeSuite 11/7/08
COCONUT - A correct-by Construction Workbench for Design and Verification of Embedded Systems 1/1/08


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