Giuseppe Di Guglielmo

GDG,  September 28, 2012
Position
Research Assistants
Mobile
+39 347 0493371
E-mail
giuseppe|diguglielmo*univr|it <== Replace | with . and * with @ to have the right email address.
Personal web page
http://www.cs.columbia.edu/~giuseppe

Modules

Modules running in the period selected: 2.
Click on the module to see the timetable and course details.

Course Name Total credits Online Teacher credits Modules offered by this teacher
Bachelor's degree in Computer Science Operating Systems (2011/2012)   12  eLearning [Laboratorio 2] (Laboratorio)
Level 1 Masters in Network Planning and Management Sistemi Multimediali di Rete (2006/2007)   5     

 

Research groups

Electronic Systems Design (ESD)
Techniques for the automatic design of electronic systems, based on formal languages and correct by construction or formally verified methodologies
Skills
Topic Description Research area
Embedded system verification Verification techniques for embedded systems at different abstraction levels, with particular emphasis on: - Static verification - Dynamic verification - Semi-formal verification - Hybrid and real-time systems Sistemi ciberfisici
Hardware - Hardware validation
Projects
Title Starting date
Verifica formale di Software modellato e generato automaticamente (Verilab - Azione I) 10/14/10
Verifica formale di Software modellato e generato automaticamente (Verilab - Azione III) 10/14/10
Verifica formale di Software modellato e generato automaticamente (Verilab - Azione V) 10/14/10
Modellazione e verifica di sistemi embedded 11/26/09
Centre of Reserach Excellence in Dependable Embedded Systems (CREDES) 10/1/09
Sviluppo degli ambienti di progettazione per sistemi embedded HIFSuite e ZigBeeSuite 11/7/08
COCONUT - A correct-by Construction Workbench for Design and Verification of Embedded Systems 1/1/08