|Wednesday||1:30 PM - 3:30 PM||laboratorio||Laboratory Laboratorio Ciberfisico|
|Friday||8:30 AM - 11:30 AM||lesson||Lecture Hall I|
The aim of this course is the presentation of some design automation techniques for embedded systems covering the entire design flow through modeling, verification, synthesis and testing. The most important design languages are introduced such as the most advanced EDA tools.
Introduction to embedded systems.
Embedded systems modeling.
Embedded systems design alternatives.
Transactional Level Modeling (TLM) by using SystemC.
Introduction to Assertion-based verification (ABV).
Embedded software design.
Register transfer level (RTL) hardware description languages (VHDL/SystemC).
Automatic synthesis from RTL designs.
The problem of testing.
The problem of dependability.
|Daniel D. Gajski||Embedded system design: modeling, synthesis and verification||Springer||2009||978-1-4419-0504-8|
|William Fornaciari, Carlo Brandolese||Sistemi Embedded - sviluppo hardware e software per sistemi dedicati (Edizione 1)||Pearson Education Italia||2007||9788871923420|
Written examination and laboratory activity report.