Introduction to DSP based Serial Links

Speaker:  Fernando De Bernardinis - eSilicon
  Tuesday, May 28, 2019 at 4:30 PM Aula Verde

We introduce the design challenge of implementing a Serializer/Deserialized (SerDes) system capable 

of sustaining a bitrate >50 Gb/s and 100Gb/s. The switch from an NRZ to a PAM-4 modulation scheme, 

with the increased equalization power required on the receive side, encourages the adoption of DSP 

based solutions to implement current and next generations long reach SerDes. There are two big 

challenges to be coped with, power consumption due to digital domain signal processing, and the 

complexity of designing the Analog Front End capable of converting A/D and D/A at the required 

sampling frequency. A holistic approach implying the codesign of the AFE and DSP, including an 

embedded software component as firmware, has been taken to provide a very efficient and powerful 

implementation in 7nm. Given the complexity of the system, the software component provides crucial 

control and configuration tasks, which include setup and optimization of the link for different 

communication speeds and modulation, as well as link monitoring and exception handling. The embedded 

nature of the application implies limited resource availability and tight interaction with analog 

and digital circuitry, which makes development and testing a team work with designers and test 

engineers. Finally, some details of the architecture and performance as presented at this year’s 

ISSCC are given, showing how both power consumption and channel length are widely improved over 

previous works.

 

About eSilicon

 

eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging 

solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus 

networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory 

compilers and I/O libraries.

 

Bio:

 

Fernando De Bernardinis received the Laurea degree in electrical engineering from the University of 

Pisa, Scuola S. Anna, Italy, in 1996, a Ph.D in Electrical Engineering from the same University in 

2000 and M.S. and Ph.D. degrees from the University of California, Berkeley, in 2001 and 2005, 

respectively. He was Assistant Professor in the Department of Information Engineering at the 

University of Pisa until he joined Marvell Italy in 2006 and eSilicon in 2017. His research 

interests include digitally assisted analog design, mixed signal system level design, architecture 

design and DSP algorithm optimization. Since 2012, he has been leading the architecture and 

algorithm design of DSP based serial links, developing 56 Gb/s and 112Gb/s generations at eSilicon.


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Publication date
May 16, 2019

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