- University of Waterloo, Canada
Tuesday, April 24, 2018
This talk presents an approach to allow simultaneous and predictable accesses to shared data for safety-critical systems deployed on multicore platforms. We propose a predictable cache coherence protocol, which mandates the use of certain invariants to ensure predictability. In particular, we enforce these invariants by augmenting the classic modify-share-invalid (MSI) protocol with transient coherence states, and minimal architectural changes. This allows us to derive worst-case latency bounds on a predictable MSI (PMSI) coherence protocol. Our analysis shows that the arbitration latency scales linearly, and the coherence latency scales quadratically with the number of cores. This emphasizes the importance of accounting for cache coherence effects on worst-case latency bounds. We implement PMSI in gem5, and execute SPLASH-2 and synthetic workloads. Results show that our approach is always within the analytical worst-case latency bounds, and that PMSI improves average-case performance by up to 4 over the next best predictable alternative.
Contact person: Nicola Bombieri
- Programme Director
- Publication date
April 16, 2018