Data- and State-Dependent Power Characterisation and Simulation of Black-Box RTL IP Components at System Level

Due to the increasing algorithmic complexity of today's embedded systems, the consideration of extra-functional properties becomes even more important. Extra-functional properties such as timing, power consumption, and temperature need to be validated against given requirements on all abstraction levels. For timing and power consumption at RT- and gate-level, several techniques are available, but there is still a lack of methods and tools for power estimation and analyses at electronic system level (ESL) and above.   
In this seminar I present my approach of a Power State Machine (PSM) model which is especially suited for modelling the power behaviour of black-box RTL IP components at ESL since it derives the power consumption by observing the I/O behaviour. Additionally, a Protocol State Machine (PrSM) was introduced to abstract the protocol behaviour from the I/O ports for the PSM. Furthermore, a mechanism is shown that allows to model data-dependent power behaviour in the PSM which can reduce the error significantly. To support the user with the characterisation of the PSM an automatic PSM synthesis was developed which is based on a given PrSM and some I/O traces with the corresponding generated gate-level power traces. To ease the manual creation of PSM models an Eclipse plug-in was implemented which supports the user in creating and optimising the PSM model. It also includes an implementation of the automatic PSM synthesis.