General and efficient SAT-based ATPG framework for multiple various faults and its application to partial logic and system synthesis

Relatore:  Masahiro Fujita - Graduate School of Engineering, The University of Tokyo
  giovedì 16 ottobre 2014 alle ore 17.00 16:45 rinfresco; 17:00 inizio seminario

We present a SAT-based automatic test pattern generationmethod by which complete test patterns for multiple faults of multiple fault models can be generated. The entire ATPG process is formulated as incremental SAT problem, which makes computations 10-50 times faster than approaches with normal non-incremental SAT solvers. Also, given initial test patterns, the required patterns for the remaining faults can be generated as extra patterns. This means we can start with generating test patterns for, say multiple stuck-at faults, and after that, the test patterns are expanded to test multiple faults of another fault models, such as toggle faults. We show various experimental results with ISCAS89 circuits, some of which are very interesting in the sense that small numbers of extra patterns are required when we expand the target fault models. We also present applications of the proposed ATPG method to logic and system synthesis where the ranges of design transformations are constrained which are represented as sorts of 

 


Luogo
Ca' Vignal 3 - Piramide, Piano 0, Sala Verde

Referente
Tiziano Villa

Data pubblicazione
30 settembre 2014

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