Heterogeneous system-on-chip (SoC) architectures are emerging as a fundamental computing platform for a variety of systems from data centers to mobile devices. Design productivity for SoC platforms depends on creating and maintaining reusable components at higher levels of abstraction and on hierarchically combining them to form optimized subsystems. While the design of a single component is important, the critical challenges are in the integration and management of many heterogeneous components, including programmable cores and specialized hardware accelerators. In addressing these challenges we sustain that communication plays an increasingly central role both at design time and run time. We propose a communication-based system-level design methodology that simplifies the design and validation of heterogeneous SoC platforms by enabling important properties like modularity, scalability, flexibility, and reusability. We also present recent results on Supervised Design-Space Exploration: this is a novel approach to leverage synthesis tools for the characterization of accelerators with respect to their power/performance tradeoffs, a key step to enable efficient design reuse across various architectures.
Strada le Grazie 15
Partita IVA 01541040232
Codice Fiscale 93009870234
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