FPGA based acceleration of pattern matching, scientific computing and verification of large LSI chips

There have been reported efforts to use FPGA chips to speed up computation in high performance computing fields. This talk shows our experiences and future
plans to accelerate logic verification for both digital and analog parts of large LSI chips.  Such verification requires speed up of pattern matching
related problems for digital parts of the designs as well as high speed circuits for floating point computation for analog parts of them. The talk
first discuss about FPGA based acceleration of computing in general with respect to general purpose or general graphic processors followed by our
results on pattern matching (bioinformatic problem as an example target) and floating point computations (Tsunami simulation as an example).  In each
case, we can realize more than 100 times speed up over general purpose processors and more than 10 times speed up over general graphic processors.  In the last
part of the talk, our plans on FPGA based emulator for both digital and analog  parts of designs are presented. Our emulator can not only simulate both digital
and analog parts of designs, it has capability to automatically infer assertions from the emulations results.  Basic architecture of the emulator is introduced.