This talk introduces the topic of technology mapping and presents an
algorithm for mapping logic networks into K-input lookup-tables (K-LUTs).
The algorithm avoids the hurdles of computing all K input cuts while
preserving the quality of the results, in terms of area and depth. The
memory and runtime of the proposed algorithm are linear in circuit size
and quite affordable even for large industrial designs. An extension of
the algorithm allows for sequential mapping, which searches the combined
space of all mappings and retimings. This leads to an average 20%
improvement in depth with a marginal area penalty, compared to
combinational mapping followed by retiming.
Strada le Grazie 15
Partita IVA 01541040232
Codice Fiscale 93009870234
© 2018 | Università degli studi di Verona | Credits