Voronoi diagrams, generalizations, and applications in VLSI manufacturing
- Evanthia Papadopoulou - IBM T. J. Watson Research Center
- Data e ora
- martedì 29 aprile 2008 alle ore 16.15 - Inizio alle 16:30, Caffè e biscotti alle 16:15.
- Ca' Vignal 3 - Piramide, Piano 0, Sala Verde
- Tiziano Villa
- Referente esterno
- Data pubblicazione
- 2 aprile 2008
The Voronoi diagram is a powerful mathematical object encoding nearest neighbor information with numerous applications in diverse areas. In this talk I will present my work on generalized Voronoi diagrams, specifically, the Hausdorff Voronoi diagram and higher order Voronoi diagrams of segments, and present applications in VLSI manufacturing. The Critical Area of a VLSI design is a measure reflecting the sensitivity of the design to random defects occurring during the chip manufacturing process. Fast and accurate critical area extraction is essential for modern VLSI manufacturing especially when Design for Manufacturability (DFM) changes are under consideration. I will address the critical area extraction problem for various types of faults such as shorts, open faults, and via blocks, using our results on generalized Voronoi diagrams. I will concentrate on my latest result on net-aware critical area extraction for open faults, based on a combination of a graph formulation and higher order Voronoi diagrams of segments. All algorithms have been integrated into a new IBM-Cadence CAD tool (Voronoi CAA) that is being widely used by IBM Microelectronics for critical area extraction and yield prediction.
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