RTL-to-RTM hierarchical abstraction e TSL-guided testbench generation

Starting date
January 2, 2013
Duration (months)
12
Departments
Computer Science
Managers or local contacts
Pravadelli Graziano

Project goals are:
- extension of the RTL to TLM abstraction mechanism in the context of RTL hierarchical descriptions;
- extension of radCHECK to automatically generate test sequences based on the test bench specification language TSL

Sponsors:

EDALab s.r.l.
Funds: assigned and managed by the department
Syllabus: ART66 - Attività Commerciale

Project participants

Luca Piccolboni
Graziano Pravadelli
Full Professor
Research areas involved in the project
Sistemi ciberfisici
Embedded and cyber-physical systems

Activities

Research facilities