The project can be divided in two main parts which face the yield improvement problem from two different points of view: the optimization of the design and the optimization of the production process.
Each part is subdivided in some subparts which represent the tasks reported in the next section. Here is presented the complete list of all parts and subparts; they will be described in depth in the following section:
- Yield improvement through cells library characterization and place&route optimization.
- identification of the placement context-dependent standard cell level yield loss mechanisms;
- characterization of a standard cell library in terms of yield;
- definition and design of a yield-aware place&route algorithm;
- integration of the place&route algorithm in the standard production flow.
- Yield, fault models and integrated circuits diagnosability.
- identification of the relationships between yield models of standard cells and fault models;
- customization of available test generators considering the fault models found in the previous step;
- study the relation between detected faults, test used to reveal them and the cells in which the faults was generated;
- design of a methodology for fault diagnosis.
Both parts of the project will also include an application phase where the two identified main techniques will be applied to real ICs provided by PDF. This application will emphasize the yield improvement achieved by the project.