Michele Lora

Foto,  May 4, 2017
Research Scholarship Holders
Ca' Vignal 2,  Floor 1,  Room 71
+39 045 802 7048
michele|lora*univr|it <== Replace | with . and * with @ to have the right email address.

Office Hours

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Modules running in the period selected: 3.
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Course Name Total credits Online Teacher credits Modules offered by this teacher
Bachelor's degree in Computer Science Computer Architecture (2016/2017)   12  eLearning (Esercitazioni)
Bachelor's degree in Computer Science Operating Systems (2016/2017)   12  eLearning [Laboratorio 2] (Laboratorio)
Bachelor's degree in Computer Science Computer Architecture (2015/2016)   12  eLearning (Esercitazioni)

Topic Description Research area
Embedded system design Design techniques for the automatic generation of embedded hardware/software starting from transactional level models (TLM) and with emphasis on: - TLM-RTL synthesis and abstraction - RTL-to-SW abstraction - TLM transactor generation - Device-driver generation - Embedded SW for multicore systems - Hardware description language-based modeling - Middleware-based design Sistemi ciberfisici
Computer systems organization - Embedded and cyber-physical systems
Title Starting date
A framework for efficient TLM modeling and simulation of smart systems 2/29/16
TOYS - TOward Industrial Smart DisplaYS - Joint Projects 2015 1/1/16

Other positions held
Michele Lora
Office Collegial Body
component Collegio Didattico di Informatica - Department Computer Science