This class introduces the fundamental algorithms for the automatic design of embedded systems, with particular emphasis on data structures to design and optimize digital systems and on automatic techniques for synthesis, verification and testing of embedded systems.
Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.
Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.
Dynamic assertion-based verification. Assertion qualification: assertion coverage, vacuum cleaning. Automatic generation of assertions.
| Author | Title | Publisher | Year | ISBN | Note |
| Gary D.Hachtel, Fabio Somenzi | Logic Synthesis and Verification Algorithms (Edizione 1) | Kluwer Academic Publishers | 1996 | 0792397460 |
The exam includes:
- a written test with exercises and open questions covering the three parts of the program
- a project chosen by the student in one of the three parts of the program, under the supervision of the related instructor
The final score is the average of the scores in the written test and in the class project.
Ariadne - 1
(pdf, en, 1146 KB, 19/10/20)
Ariadne - 2 (Progetti)
(pdf, it, 117 KB, 22/10/20)
Calendario dell'insegnamento
(xslx, it, 13 KB, 08/10/20)
Sintesi Logica - Esercitazioni
(pdf, en, 294 KB, 30/09/20)
Sintesi Logica - Laboratorio CUDD
(x-gzip, en, 4636 KB, 06/11/20)
Sintesi Logica - Presentazione CUDD
(pdf, it, 427 KB, 05/11/20)
Sintesi Logica - Presentazione Espresso
(pdf, en, 574 KB, 22/10/20)
Sintesi Logica - Presentazione SIS
(pdf, it, 1478 KB, 22/10/20)
Sintesi Logica - Teoria
(x-gzip, en, 1965 KB, 30/09/20)
