The course introduces the fundamental methodologies for the automatic design of embedded systems, with particular emphasis on algorithms for synthesis, verification and testing.
Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.
Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.
Assertion coverage, vacuum cleaning, automatic generation of checkers.
Written examination (ON/OFF) plus a project chosen in one of the three main areas covered in the class.
Strada le Grazie 15
VAT number 01541040232
Italian Fiscal Code 93009870234
© 2021 | Verona University | Credits