| Day | Time | Type | Place | Note |
|---|---|---|---|---|
| Thursday | 11:30 AM - 1:30 PM | lesson | Lecture Hall C | |
| Friday | 8:30 AM - 11:30 AM | lesson | Lecture Hall C |
The course introduces the fundamental methodologies for the automatic design of embedded systems, with particular emphasis on algorithms for synthesis, verification and testing.
Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.
Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.
Assertion coverage, vacuum cleaning, automatic generation of checkers.
Written examination (ON/OFF) plus a project chosen in one of the three main areas covered in the class.
Calendario del corso
(pdf, it, 30 KB, 31/10/10)
Presentazione del corso
(pdf, it, 839 KB, 31/10/10)
Sintesi logica - Esercitazioni
(pdf, it, 169 KB, 31/10/10)
Sintesi logica - Teoria
(x-gzip, en, 1733 KB, 31/10/10)
