Design automation of embedded systems (2009/2010)

Course code
Name of lecturers
Tiziano Villa, Franco Fummi, Graziano Pravadelli
Tiziano Villa
Number of ECTS credits allocated
Other available courses
Academic sector
Language of instruction
1st Semester dal Oct 1, 2009 al Jan 31, 2010.

Lesson timetable

1st Semester
Day Time Type Place Note
Tuesday 10:30 AM - 1:30 PM lesson Lecture Hall F  
Thursday 12:30 PM - 2:30 PM lesson Lecture Hall B  

Learning outcomes

The course introduces the fundamental methodologies for the automatic design of embedded systems, with particular emphasis on algorithms for synthesis, verification and testing.


Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.

Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.

Assertion coverage, vacuum cleaning, automatic generation of checkers.

Assessment methods and criteria

Written examination (ON/OFF) plus a project chosen in one of the three main areas covered in the class.

Teaching aids