A growing demand for both high performance and energy efficiency characterizes embedded systems for most applications domains, including smart-phones, automotive electronics, medical and military applications. Satisfying this demand, however, is becoming increasingly harder due to the combination of two main causes: the limited parallelism that can be extracted from most software applications and the end of Dennard's constant-field scaling, which has made power, and not the number of transistors, the principal factor limiting further improvements in computing performance. In other words, the semiconductor industry has reached an age when scaling up the number of parallel processing cores on chip gives diminishing returns while the number of transistors that can be potentially integrated on a die is much larger than the number that can be active simultaneously. To cope with these issues, designers are building systems-on-chip (SoC) based on multi-core architectures that are increasingly heterogeneous. They combine a few processor cores with many hardware blocks, each specialized to execute a target computational kernel very efficiently. These so-called accelerators are activated only when needed. When idle, they don't add any burden to the limited on-chip power budget. Several additional challenges reside in the SoC design, integration and programming. This talk propose our vision for the next SoC generation that addresses these challenges: Embedded Scalable Platforms (ESP). Key aspects of ESP are regularity, flexibility and specialization. In addition during the talk we present recent methodologies for the optimization of accelerator communication and local memories.
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