Design automation of embedded systems (2019/2020)



Course code
4S02912
Credits
6
Coordinator
Tiziano Villa
Academic sector
INF/01 - INFORMATICS
Language of instruction
Italian
Teaching is organised as follows:
Activity Credits Period Academic staff Timetable
Teoria 3 I semestre Franco Fummi, Graziano Pravadelli, Tiziano Villa

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Laboratorio 3 I semestre Franco Fummi, Graziano Pravadelli, Tiziano Villa

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Learning outcomes

This class introduces the fundamental algorithms for the automatic design of embedded systems, with particular emphasis on data structures to design and optimize digital systems and on automatic techniques for synthesis, verification and testing of embedded systems.

Syllabus

Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.

Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.

Dynamic assertion-based verification. Assertion qualification: assertion coverage, vacuum cleaning. Automatic generation of assertions.

Assessment methods and criteria

The exam includes:
- a written test with exercises and open questions covering the three parts of the program
- a project chosen by the student in one of the three parts of the program, under the supervision of the related instructor

The final score is the average of the scores in the written test and in the class project.

Teaching aids
Title Format (Language, Size, Publication date)
Calendario delle Lezioni  vnd.ms-excelvnd.ms-excel (it, 28 KB, 14/10/19)
Documenti per progetti con Ariadne  x-gzipx-gzip (it, 917 KB, 30/10/19)
Nota per sorgenti Espresso e SIS plain plain (it, 0 KB, 31/10/19)
Sintesi Logica - Esercitazioni  pdfpdf (it, 286 KB, 14/10/19)
Sintesi Logica - Laboratorio CUDD  x-gzipx-gzip (it, 1560 KB, 31/10/19)
Sintesi Logica - Presentazione CUDD  pdfpdf (it, 427 KB, 31/10/19)
Sintesi Logica - Presentazione Espresso  pdfpdf (it, 574 KB, 31/10/19)
Sintesi Logica - Presentazione SIS  pdfpdf (it, 1478 KB, 31/10/19)
Sintesi Logica - Teoria  x-gzipx-gzip (en, 1965 KB, 14/10/19)