Design automation of embedded systems (2016/2017)

Course code
Name of lecturers
Tiziano Villa, Franco Fummi, Graziano Pravadelli
Tiziano Villa
Number of ECTS credits allocated
Academic sector
Language of instruction
I sem. dal Oct 3, 2016 al Jan 31, 2017.

Lesson timetable

I sem.
Day Time Type Place Note
Monday 2:30 PM - 3:30 PM laboratorio Laboratory Laboratorio Ciberfisico from Dec 19, 2016  to Jan 31, 2017
Monday 3:30 PM - 5:30 PM laboratorio Laboratory Laboratorio Ciberfisico  
Tuesday 8:30 AM - 11:30 AM lesson Laboratory Laboratorio Ciberfisico  

Learning outcomes

The course introduces the fundamental algorithms for the automatic design of embedded systems, with particular emphasis on data structures to design and optimize digital systems and on automatic techniques for synthesis, verification and testing of embedded systems.


Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.

Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.

Dynamic assertion-based verification. Assertion qualification: assertion coverage, vacuum cleaning. Automatic generation of assertions.

Assessment methods and criteria

The exam includes:
- a written test with exercises and open questions covering the three parts of the program
- a project chosen by the student in one of the three parts of the program, under the supervision of the related instructor

Teaching aids


Student opinions - 2016/2017