Embedded systems design (2016/2017)

Course code
Name of lecturer
Franco Fummi
Franco Fummi
Number of ECTS credits allocated
Academic sector
Language of instruction
I sem. dal Oct 3, 2016 al Jan 31, 2017.

Lesson timetable

I sem.
Day Time Type Place Note
Wednesday 1:30 PM - 3:30 PM laboratorio Laboratory Laboratorio Ciberfisico from Oct 10, 2016  to Jan 31, 2017
Friday 8:30 AM - 11:30 AM lesson Lecture Hall I  

Learning outcomes

The aim of this course is the presentation of some design automation techniques for embedded systems covering the entire design flow through modeling, verification, synthesis and testing. The most important design languages are introduced such as the most advanced EDA tools.


Introduction to embedded systems.

Embedded systems modeling.

Embedded systems design alternatives.

System-level design.

Transactional Level Modeling (TLM) by using SystemC.

Introduction to Assertion-based verification (ABV).

Platform-based design.

Embedded software design.

HW/SW/NET co-simulation.

Register transfer level (RTL) hardware description languages (VHDL/SystemC).

Automatic synthesis from RTL designs.

The problem of testing.

The problem of dependability.

Reference books
Author Title Publisher Year ISBN Note
Daniel D. Gajski Embedded system design: modeling, synthesis and verification Springer 2009 978-1-4419-0504-8
Soonhoi Ha, Jürgen Teich Handbook of Hardware/Software Codesign (Edizione 1) Springer Netherlands 2017 ISBN 978-94-017-7266-2

Assessment methods and criteria

Written examination and laboratory activity report.

Teaching aids


Student opinions - 2016/2017

Statistics about transparency requirements (Attuazione Art. 2 del D.M. 31/10/2007, n. 544)

Data from AA 2016/2017 are not available yet