Design automation of embedded systems (2011/2012)

Course code
Name of lecturers
Tiziano Villa, Franco Fummi, Graziano Pravadelli
Tiziano Villa
Number of ECTS credits allocated
Academic sector
Language of instruction
I semestre dal Oct 3, 2011 al Jan 31, 2012.

Lesson timetable

I semestre
Day Time Type Place Note
Thursday 11:30 AM - 1:30 PM lesson Lecture Hall C  
Friday 8:30 AM - 11:30 AM lesson Lecture Hall C  

Learning outcomes

The course introduces the fundamental methodologies for the automatic design of embedded systems, with particular emphasis on algorithms for synthesis, verification and testing.


Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.

Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.

Assertion coverage, vacuum cleaning, automatic generation of checkers.

Assessment methods and criteria

Written examination (ON/OFF) plus a project chosen in one of the three main areas covered in the class.

Teaching aids