Design automation of embedded systems (2010/2011)

Course code
Name of lecturers
Tiziano Villa, Franco Fummi, Graziano Pravadelli
Tiziano Villa
Number of ECTS credits allocated
Academic sector
Language of instruction
I semestre dal Oct 4, 2010 al Jan 31, 2011.

Lesson timetable

I semestre
Day Time Type Place Note
Thursday 11:30 AM - 1:30 PM lesson Lecture Hall C  
Friday 8:30 AM - 11:30 AM lesson Lecture Hall C  

Learning outcomes

The course introduces the fundamental methodologies for the automatic design of embedded systems, with particular emphasis on algorithms for synthesis, verification and testing.


Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.

Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.

Assertion coverage, vacuum cleaning, automatic generation of checkers.

Assessment methods and criteria

Written examination (ON/OFF) plus a project chosen in one of the three main areas covered in the class.

Teaching aids


Statistics about transparency requirements (Attuazione Art. 2 del D.M. 31/10/2007, n. 544)

Outcomes Exams Outcomes Percentages Average Standard Deviation
Positive 50.0% 30 0
Rejected --
Absent 50.0%
Ritirati --
Canceled --
Distribuzione degli esiti positivi
18 19 20 21 22 23 24 25 26 27 28 29 30 30 e Lode
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 40.0% 60.0%

Data from AA 2010/2011 based on 10 students. I valori in percentuale sono arrotondati al numero intero più vicino.