Embedded systems design (2010/2011)

Course code
4S02911
Name of lecturer
Franco Fummi
Coordinator
Franco Fummi
Number of ECTS credits allocated
6
Other available courses
Academic sector
ING-INF/05 - INFORMATION PROCESSING SYSTEMS
Language of instruction
Italian
Period
II semestre dal Mar 1, 2011 al Jun 15, 2011.

Lesson timetable

II semestre
Day Time Type Place Note
Thursday 3:30 PM - 5:30 PM lesson Lecture Hall G from Mar 11, 2011  to Jun 15, 2011
Friday 8:30 AM - 9:30 AM lesson Lecture Hall I  
Friday 9:30 AM - 11:30 AM laboratorio Laboratory Alfa  

Learning outcomes

The aim of this course is the presentation of some design automation techniques for embedded systems covering the entire design flow through modeling, verification, synthesis and testing. The most important design languages are introduced such as the most advanced EDA tools.

Syllabus

Introduction to embedded systems.

Embedded systems modeling.

Embedded systems design alternatives.

System-level design.

Transactional Level Modeling (TLM) by using SystemC.

Assertion-based verification.

Platform-based design.

Embedded software design.

HW/SW/NET co-simulation.

Register transfer level (RTL) hardware description languages (VHDL/SystemC).

Automatic synthesis from RTL designs.

The problem of testing.

The problem of dependability.

Reference books
Author Title Publisher Year ISBN Note
Daniel D. Gajski Embedded system design: modeling, synthesis and verification Springer 2009 978-1-4419-0504-8 Methodologies and languages for embedded systems design
Franco Fummi, Mariagiovanna Sami, Cristina Silvano Progettazione Digitale (Edizione 2) McGraw-Hill 2007 8838663521 In relazione alla progettazione basata su HDL
William Fornaciari, Carlo Brandolese Sistemi Embedded - sviluppo hardware e software per sistemi dedicati (Edizione 1) Pearson Education Italia 2007 9788871923420 Descrizione generale della progettazione di sistemi embedded

Assessment methods and criteria

Written examination and practical design.

Teaching aids

Documents

Statistics about transparency requirements (Attuazione Art. 2 del D.M. 31/10/2007, n. 544)

Statistics
Outcomes Exams Outcomes Percentages Average Standard Deviation
Positive 72.22% 29 2
Rejected 5.55%
Absent 16.66%
Ritirati 5.55%
Canceled --
Distribuzione degli esiti positivi
18 19 20 21 22 23 24 25 26 27 28 29 30 30 e Lode
0.0% 0.0% 0.0% 0.0% 7.6% 0.0% 0.0% 0.0% 7.6% 7.6% 7.6% 15.3% 15.3% 38.4%

Data from AA 2010/2011 based on 18 students. I valori in percentuale sono arrotondati al numero intero più vicino.